The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Nov. 09, 2023
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Sung Lae Oh, Icheon-si, KR;

Sang Woo Park, Icheon-si, KR;

Dong Hyuk Chae, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2005.12); H01L 21/768 (2005.12); H01L 23/528 (2005.12); H10B 69/00 (2022.12);
U.S. Cl.
CPC ...
H01L 23/5226 (2012.12); H01L 21/76816 (2012.12); H01L 23/5283 (2012.12); H10B 69/00 (2023.01);
Abstract

A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.


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