The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Jan. 03, 2024
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Kyonghwan Oh, Yongin-si, KR;

Taehoon Kwon, Yongin-si, KR;

Mina Kim, Yongin-si, KR;

Kyung-Hoon Kim, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2005.12);
U.S. Cl.
CPC ...
G09G 3/2096 (2012.12); G09G 2300/0426 (2012.12); G09G 2300/0819 (2012.12); G09G 2300/0852 (2012.12); G09G 2300/0861 (2012.12); G09G 2310/0267 (2012.12); G09G 2310/0291 (2012.12); G09G 2310/08 (2012.12);
Abstract

A driver is disposed in a display panel, and includes a plurality of stages. At least one stage of the plurality of stages includes an input circuit which transfers an input signal to a first node in response to at least one of a clock signal and an inverted clock signal, and inverters which generate an output signal based on a voltage of the first node. At least one of the inverters includes a p-type metal-oxide-semiconductor ('PMOS') transistor and an n-type metal-oxide-semiconductor (“NMOS”) transistor connected in series between a line transferring a relatively high gate voltage and a line transferring a relatively low gate voltage. A first active region of the PMOS transistor includes a material different from a material of a second active region of the NMOS transistor.


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