The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Jun. 03, 2021
Applicant:

Amazon Technologies, Inc., Seattle, WA (US);

Inventors:

Vinod Sharma, Menlo Park, CA (US);

Yao Wang, Newark, CA (US);

Xingyu Zhou, Santa Clara, CA (US);

Yanming Wang, Santa Clara, CA (US);

Yong Wu, Shenzhen, CN;

Rui Li, Salt Lake City, UT (US);

Assignee:

Amazon Technologies, Inc., Seattle, WA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/10 (2005.12); G06F 9/38 (2017.12); G06N 3/04 (2022.12);
U.S. Cl.
CPC ...
G06N 3/10 (2012.12); G06F 9/38873 (2023.07); G06N 3/04 (2012.12);
Abstract

Techniques for optimizing and deploying deep neural network (CNN) machine learning models for inference using static analysis are described. A method includes obtaining a deep neural network (DNN) machine learning (ML) model, generating an intermediate representation for the ML model, the intermediate representation including one or more nodes corresponding to one or more operators utilized by the ML model, identifying, for at least one node of the intermediate representation, an optimized schedule for at least one operator corresponding to the at least one node using a static analysis that is based on a hardware-specific cost model, generating an optimized intermediate representation using the optimized schedule that is optimized for execution on a hardware platform, and generating code corresponding to the ML model based at least in part on the optimized intermediate representation, wherein the code is specific to the hardware platform.


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