Data value prediction and pre-alignment based on prefetched predicted memory access address

Abstract

An apparatus with prefetching capabilities is provided in order to produce predictions of a memory address to be accessed by a load instruction in the future. An additional special cache is provided where pre-aligned data can be stored based on that prediction. When that load instruction is eventually received, the prediction can be confirmed and the pre-aligned data returned and loaded into a register file. In accordance with these techniques, the load instruction does not need to access the memory system nor perform alignment of the data before loading it into the register file. Hence the load instruction is performed faster than when loading data via a memory access. Further precautionary functionalities are also provided to manage the pre-aligned data to avoid the possibility of data corruption after a substantive change occurs to the state of memory.