The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Jul. 08, 2022
Applicant:

Cornami, Inc., Santa Clara, CA (US);

Inventors:

Morris Jacob Creeger, Santa Clara, CA (US);

Tianfang Liu, Santa Clara, CA (US);

Frederick Furtek, Santa Clara, CA (US);

Paul L. Master, Santa Clara, CA (US);

Assignee:

Cornami, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/16 (2005.12); G06F 7/48 (2005.12); G06F 8/41 (2017.12); G06F 9/38 (2017.12); G06F 17/14 (2005.12);
U.S. Cl.
CPC ...
G06F 9/3812 (2012.12); G06F 7/4806 (2012.12); G06F 8/4436 (2012.12); G06F 17/142 (2012.12);
Abstract

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.


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