The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Dec. 08, 2022
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Dong Jae Jung, Icheon-si, KR;

Jae Woong Kim, Icheon-si, KR;

Shin Won Seo, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2005.12); G11C 16/04 (2005.12); G11C 16/16 (2005.12);
U.S. Cl.
CPC ...
G06F 3/0619 (2012.12); G06F 3/0629 (2012.12); G06F 3/0679 (2012.12); G11C 16/0483 (2012.12); G11C 16/16 (2012.12);
Abstract

A semiconductor memory device, and a method of operating the same, includes a memory block including a plurality of pages, a read and write circuit configured to apply a first bit line voltage to a selected bit line corresponding to a selected memory cell and apply a second bit line voltage having a potential lower than that of the first bit line voltage to an unselected bit line during detrap operation, a voltage generation circuit configured to generate a first set voltage, a second set voltage, and a pass voltage during the detrap operation, and an address decoder configured to apply the first set voltage to a selected word line corresponding to the selected page and apply the second set voltage having a potential higher than that of the first set voltage to unselected word lines, during the detrap operation.


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