The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Jan. 28, 2022
Applicant:

Medtronic, Inc., Minneapolis, MN (US);

Inventors:

Mark E. Henschel, Phoenix, AZ (US);

Andrew J. Ries, Lino Lakes, MN (US);

Songhua Shi, Tempe, AZ (US);

Jemmy Sutanto, Scottsdale, AZ (US);

Lea Ann Nygren, Bloomington, MN (US);

Assignee:

Medtronic, Inc., Minneapolis, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
A61N 1/375 (2005.12); H01R 12/52 (2010.12); H01R 43/20 (2005.12);
U.S. Cl.
CPC ...
A61N 1/3754 (2012.12); A61N 1/3758 (2012.12); H01R 12/52 (2012.12); H01R 43/205 (2012.12); A61N 1/37512 (2017.07);
Abstract

Various embodiments of an electronics module and an implantable medical device that includes such module are disclosed. The module includes a feedthrough header assembly having a conductive header that includes a conductive inner surface, an outer surface, and a contact disposed on the inner surface and electrically connected to the header; and a feedthrough pin disposed within a via that extends through the header. The module further includes an electronic layer having a substrate and an electronic component disposed on or within the substrate. The electronic component is electrically connected to the contact of the conductive header such that the electronic component is electrically connected to the header. A major surface of the substrate of the electronic layer faces the conductive inner surface of the header without any intervening nonconductive layers disposed between the major surface of the substrate and the conductive inner surface of the header.


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