Systems and methods for using a packet processing pipeline circuit to extend the capabilities of rate limiter circuits

Abstract

The rate limiter circuits in the packet processing chip of a NIC are a limited hardware resource that may limit the number of workloads that can be run on a server. Some such chips include an egress packet processing pipeline circuit and a second packet processing pipeline circuit that prepares work for the egress pipeline circuit. Some of the stages of the second pipeline circuit can be configured as a first limiter and a second limiter that implement aspects of different rate limiters such as IOPS limiters, bandwidth limiters, etc. Another pipeline stage can use the outputs of the different rate limiters to make a limiting decision that is written into one of the rate limiter circuits. The second pipeline circuit is thereby implementing virtualized rate limiters where one of the rate limiter circuits performs the rate limiting for the virtualized rate limiters.