The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2025

Filed:

May. 23, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Eun Chu Oh, Hwaseong-si, KR;

Junyeong Seok, Seoul, KR;

Younggul Song, Hwaseong-si, KR;

Wijik Lee, Suwon-si, KR;

Byungchul Jang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/42 (2005.12); G11C 7/10 (2005.12); G11C 29/44 (2005.12); G06F 3/06 (2005.12); G06F 11/10 (2005.12); G06F 12/02 (2005.12); G11C 29/12 (2005.12); G11C 29/52 (2005.12); H03M 13/05 (2005.12); H03M 13/29 (2005.12);
U.S. Cl.
CPC ...
G11C 29/42 (2012.12); G11C 7/1039 (2012.12); G11C 7/1069 (2012.12); G11C 7/1096 (2012.12); G11C 29/4401 (2012.12); G06F 3/0679 (2012.12); G06F 11/1044 (2012.12); G06F 12/0246 (2012.12); G11C 2029/1202 (2012.12); G11C 29/52 (2012.12); H03M 13/05 (2012.12); H03M 13/2906 (2012.12); H03M 13/2945 (2012.12);
Abstract

A storage device includes a nonvolatile memory device including a memory cell array and a storage controller to control the nonvolatile memory device. The memory cell array includes word-lines, memory cells and word-line cut regions dividing the word-lines into memory blocks. The storage controller includes an error correction code (ECC) engine including an ECC encoder and a memory interface. The ECC encoder performs a first ECC encoding operation on each of sub data units in user data to generate parity bits and generate a plurality of ECC sectors, selects outer cell bits to be stored in outer cells to constitute an outer ECC sector including the outer cell bits and performs a second ECC encoding operation on the outer ECC sector to generate outer parity bits. The memory interface transmits, to the nonvolatile memory device, a codeword set including the ECC sectors and the outer parity bits.


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