Memory device and operating method for target refresh operation based on number of accesses

Abstract

A semiconductor memory device includes: a memory cell region including normal cells and row-hammer cells coupled to each of a plurality of rows, wherein the row-hammer cells of a selected row are suitable for storing first data and second data, the first data representing a number of accesses to the selected row and the second data denoting whether to refresh second adjacent rows of the selected row; and a refresh control circuit suitable for: selecting a sampling address based on the first data read from a row corresponding to an input address when an active command is inputted, determining, in response to a refresh command, whether to refresh first adjacent rows of a target row corresponding to the sampling address, and determining, in response to the refresh command, whether to refresh second adjacent rows of the target row based on the second data read from the target row.