The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2025

Filed:

Mar. 11, 2022
Applicants:

Sheida Gohardehi, Waterloo, CA;

Manoj Sachdev, Waterloo, CA;

Qing LI, Cupertino, CA (US);

William Wong, Waterloo, CA;

Inventors:

Sheida Gohardehi, Waterloo, CA;

Manoj Sachdev, Waterloo, CA;

Qing Li, Cupertino, CA (US);

William Wong, Waterloo, CA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2015.12); H01L 29/786 (2005.12);
U.S. Cl.
CPC ...
G09G 3/3233 (2012.12); G09G 2300/0465 (2012.12); G09G 2300/0852 (2012.12); G09G 2310/0286 (2012.12); G09G 2310/08 (2012.12); G09G 2330/021 (2012.12); H01L 29/78669 (2012.12);
Abstract

The disclosure is directed at a CMOS-like logic gate including a set of thin-film transistors (TFTs), the set of TFTs including a subset of pull down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacitor; wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; and wherein at least one of the subset of pull-down TFTs is connected to a first input.


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