The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2025

Filed:

Aug. 02, 2023
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Zhenni Wan, San Jose, CA (US);

Bo Lei, San Jose, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2005.12);
U.S. Cl.
CPC ...
G06F 3/0619 (2012.12); G06F 3/0659 (2012.12); G06F 3/0679 (2012.12);
Abstract

A memory device includes control circuitry configured to perform an erase operation to erase memory cells of a memory block and perform an erase verify operation to verify whether the memory cells were sufficiently erased. To perform the erase operation, the control circuitry is configured to supply a first erase voltage pulse, perform the erase verify operation subsequent to supplying the first erase voltage pulse, subsequent to the erase verify operation, supply a first bias voltage to a first one of a plurality of memory strings and a second bias voltage different than the first bias voltage to a second one of a plurality of memory strings, and, while supplying the first and second bias voltages, supply a second erase voltage pulse. The second bias voltage is configured to inhibit the second erase voltage pulse supplied to the memory cells of the second one of the plurality of memory strings.


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