Hardware-based save-and-restore controller

Abstract

This document describes systems and techniques for a hardware-based save-and-restore controller in an SoC. The described systems and techniques can automatically save and restore access control configurations (e.g., register states) of IP subsystems during a power-down and a power-up sequence, respectively. The save operation is initiated by a local save-and-restore (L SAR) controller and performed by the IP subsystems writing the configuration values to a central save-and-restore (C-SAR) controller before powering down a power domain. The C-SAR controller saves the configuration information in a memory located in an always-on power domain. The described systems and techniques initiate, via the L SAR controller, a restore operation as part of the power-up sequence. In this way, the described systems and techniques provide scalable save-and-restore services, support a large number of power domains, and allow a variable number of access control configurations to be saved and restored.