The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2025

Filed:

Nov. 18, 2024
Applicants:

Montana State University, Bozeman, MT (US);

Resilient Computing, Llc, Bozeman, MT (US);

Inventors:

Brock Jerome LaMeres, Bozeman, MT (US);

Christopher Michel Major, Belgrade, MT (US);

Hezekiah Ajax Austin, Bozeman, MT (US);

Assignees:

MONTANA STATE UNIVERSITY, Bozeman, MT (US);

RESILIENT COMPUTING, LLC, Bozeman, MT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2005.12); G06F 11/20 (2005.12);
U.S. Cl.
CPC ...
G06F 11/2041 (2012.12); G06F 2201/805 (2012.12);
Abstract

A fault-tolerant computer system includes a plurality of redundant processor cores configured to simultaneously execute identical sets of processor-executable instructions, and a coprocessor component including a data storage component and a configurable logic region, where the plurality of processor cores are configured with processor-executable instructions to perform operations including configuring the configurable logic region of the coprocessor component with a first coprocessing module, and controlling the first coprocessing module to perform first processing operations on data located in the data storage component. In various embodiments, the redundant processor cores and the coprocessor component may be implemented on an FPGA, and the redundant processor cores may be configured to swap out different coprocessing modules using Partial Reconfiguration (PR) to perform data processing algorithms using hardware acceleration. Embodiments of the fault-tolerant computer system may be utilized in radiation intensive environments, such as in outer space.


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