The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Oct. 26, 2023
Applicant:

Xiamen Tianma Micro-electronics Co., Ltd., Xiamen, CN;

Inventors:

Qingjun Lai, Xiamen, CN;

Yihua Zhu, Xiamen, CN;

Yong Yuan, Xiamen, CN;

Ping An, Xiamen, CN;

Zhaokeng Cao, Xiamen, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/3225 (2015.12); H10D 86/40 (2024.12); H10D 86/60 (2024.12); H10K 59/121 (2022.12);
U.S. Cl.
CPC ...
H10D 86/60 (2024.12); G09G 3/3225 (2012.12); H10D 86/431 (2024.12); H10D 86/471 (2024.12); G09G 2300/0426 (2012.12); G09G 2300/0465 (2012.12); G09G 2300/0814 (2012.12); G09G 2300/0842 (2012.12); H10D 86/423 (2024.12); H10K 59/1213 (2023.01);
Abstract

A display panel includes a base substrate, a first transistor and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes an oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. The first transistor further includes a third gate electrode. Along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, and D1<D3.


Find Patent Forward Citations

Loading…