The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Jun. 26, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Junghwan Chun, Anyang-si, KR;

Hongsik Shin, Seoul, KR;

Koungmin Ryu, Hwaseong-si, KR;

Bongkwan Baek, Seoul, KR;

Jongmin Baek, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2024.12); H01L 21/02 (2005.12); H10D 30/01 (2024.12); H10D 30/43 (2024.12); H10D 62/10 (2024.12); H10D 64/01 (2024.12);
U.S. Cl.
CPC ...
H10D 30/6729 (2024.12); H01L 21/02603 (2012.12); H10D 30/014 (2024.12); H10D 30/031 (2024.12); H10D 30/43 (2024.12); H10D 30/6735 (2024.12); H10D 30/6757 (2024.12); H10D 62/121 (2024.12); H10D 64/01 (2024.12); H10D 64/017 (2024.12);
Abstract

A semiconductor device includes an active region extending on a substrate in a first direction, a gate structure including a gate electrode extending on the substrate in a second direction and traversing the active region, a spacer structure extending on opposing sidewalls of the gate electrode in the second direction, and a capping layer on the gate electrode and the spacer structure, a source/drain region on the active region adjacent the gate structure, and a first contact plug connected to the source/drain region and a second contact plug connected to the gate structure. The capping layer includes a lower capping layer and an upper capping layer on the lower capping layer, and the second contact plug penetrates through the capping layer, is connected to the gate electrode and includes a convex sidewall penetrating into the upper capping layer.


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