The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Aug. 08, 2021
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Hiroyuki Ogawa, Nagoya, JP;

Hardwell Chibvongodze, Hiratsuka, JP;

Zhixin Cui, Nagoya, JP;

Rajdeep Gautam, Nagoya, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2022.12); G11C 16/04 (2005.12); G11C 16/08 (2005.12); G11C 16/24 (2005.12); H01L 23/522 (2005.12); H01L 23/528 (2005.12); H10B 41/10 (2022.12); H10B 41/27 (2022.12); H10B 41/35 (2022.12); H10B 41/40 (2022.12); H10B 43/10 (2022.12); H10B 43/35 (2022.12); H10B 43/40 (2022.12); H10B 43/50 (2022.12);
U.S. Cl.
CPC ...
H10B 43/27 (2023.01); G11C 16/0483 (2012.12); G11C 16/08 (2012.12); G11C 16/24 (2012.12); H01L 23/5226 (2012.12); H01L 23/5283 (2012.12); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01);
Abstract

A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.


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