The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Jan. 29, 2024
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Geoffrey C. Gardner, West Lafayette, IN (US);

Sergei V. Gronin, West Lafayette, IN (US);

Raymond L. Kallaher, West Lafayette, IN (US);

Michael James Manfra, West Lafayette, IN (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2005.12); H01L 21/02 (2005.12); H01L 21/321 (2005.12);
U.S. Cl.
CPC ...
H01L 21/02603 (2012.12); H01L 21/02304 (2012.12); H01L 21/3212 (2012.12);
Abstract

The present disclosure relates to a method of manufacturing a nanowire structure. According to an exemplary process, a substrate is firstly provided. An intact buffer region is formed over the substrate, and a sacrificial top portion of the intact buffer region is eliminated to provide a buffer layer with a planarized top surface. Herein, the planarized top surface has a vertical roughness below 10 Å. Next, a patterned mask with an opening is formed over the buffer layer, such that a portion of the planarized top surface of the buffer layer is exposed. A nanowire is formed over the exposed portion of the planarized top surface of the buffer layer through the opening of the patterned mask. The buffer layer is configured to have a lattice constant that provides a transition between the lattice constant of the substrate and the lattice constant of the nanowire.


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