The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

May. 12, 2024
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Naoya Tokiwa, Fujisawa Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/16 (2005.12); G11C 16/04 (2005.12); G11C 16/26 (2005.12); G11C 16/34 (2005.12); G11C 16/06 (2005.12); G11C 16/08 (2005.12); G11C 16/10 (2005.12);
U.S. Cl.
CPC ...
G11C 16/16 (2012.12); G11C 16/0466 (2012.12); G11C 16/0483 (2012.12); G11C 16/26 (2012.12); G11C 16/3445 (2012.12); G11C 16/06 (2012.12); G11C 16/08 (2012.12); G11C 16/10 (2012.12);
Abstract

A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.


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