Memory device with single-transistor dram cells with no capacitors, and memory cells stacked in the vertical direction using gate-all-around (gaa) technology

Abstract

A first insulating layeris disposed on a substrate. N+ layersare separated from the insulating layer and in directions horizontal and vertical to the substrate. P layerscontact the n+ layersand extend in the horizontal direction. N+ layerscontact the p layers. Gate insulating layerscover the p layersand part of the n+ layersand. Second gate conductor layersare electrically separated from a first gate conductor layercontacting the gate insulating layers. A conductor layercontacts the n+ layers. A conductor layercontacts the n+ layers. A second insulating layercontacts the first gate conductor layer, the n+ layers, and the conductor layer. A third insulating layercontacts the second gate conductor layers, the n+ layers, and the conductor layer