Semiconductor memory device and operating method thereof

Abstract

A semiconductor memory device includes: a memory cell region including a plurality of cell mats in each of which a plurality of rows are disposed, each row coupled to normal cells and row-hammer cells; a repair control circuit suitable for generating a pairing flag denoting whether a cell mat in which an active row corresponding to an active address is disposed, is repaired with another cell mat; and a refresh control circuit suitable for: selecting, when an active command is inputted, a sampling address based on first and second data read from the row-hammer cells of the active row, refreshing, when a target refresh command is inputted, one or more adjacent rows to a target row corresponding to the sampling address, and selectively refreshing, when the target refresh command is inputted, one or more adjacent rows to a paired row of the target row according to the pairing flag.