The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Feb. 29, 2024
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Dongmyoung Kim, Paju-si, KR;

HongJae Shin, Paju-si, KR;

YongHo Kim, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/32 (2015.12); G09G 3/3266 (2015.12); H10K 59/121 (2022.12);
U.S. Cl.
CPC ...
G09G 3/3266 (2012.12); G09G 3/32 (2012.12); H10K 59/1216 (2023.01); G09G 2300/0426 (2012.12); G09G 2300/0842 (2012.12); G09G 2310/0286 (2012.12); G09G 2310/0289 (2012.12); G09G 2310/0291 (2012.12); G09G 2330/04 (2012.12);
Abstract

A display device and a gate driving panel circuit including the same are discussed. The gate driving panel circuit in an example includes an output buffer block configured to receive a clock signal and output a scan signal, and a logic block configured to control respective voltages of a Q node and a QB node electrically connected to the output buffer block. The output buffer block includes a pull-up transistor disposed between a clock node to which the clock signal is input and an output node to which the scan signal is output, and a pull-down transistor disposed between a gate low voltage node to which a gate low voltage is applied and the output node. A gate node of the pull-up transistor is electrically connected to the Q node.


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