The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Jul. 24, 2023
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Hong Suh, Palo Alto, CA (US);

Sumti Jairath, Palo Alto, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/80 (2005.12); G06F 9/30 (2017.12); G06F 9/38 (2017.12); G06F 15/78 (2005.12);
U.S. Cl.
CPC ...
G06F 15/80 (2012.12); G06F 9/30036 (2012.12); G06F 9/3836 (2012.12); G06F 15/7871 (2012.12);
Abstract

A placer and router for an iterative placement and routing of a sorted operation unit graph on a reconfigurable processor is presented as well as a method of operating a placer and router for an iterative placement and routing of a sorted operation unit graph on a reconfigurable processor. The placer and router is configured to receive an architectural specification of the reconfigurable processor and the sorted operation unit graph having an ordered sequence of nodes and edges that interconnect nodes in the ordered sequence of nodes. The placer and router is further configured to iteratively assign nodes of the sorted operation unit graph to locations on the reconfigurable processor followed by an assignment of edges that connect nodes that were assigned in the current iteration and nodes that were assigned in previous iterations to interconnection resources of the reconfigurable processor.


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