The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Nov. 01, 2023
Applicant:

Melexis Technologies NV, Tessenderlo, BE;

Inventors:

Francois Piette, Tessenderlo, BE;

Cliff De Locht, Tessenderlo, BE;

Axel Fanget, Bevaix, CH;

Andreas Ott, Erfurt, DE;

Andreas Laute, Erfurt, DE;

Thomas Freitag, Erfurt, DE;

Assignee:

MELEXIS TECHNOLOGIES NV, Tessenderlo, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2005.12);
U.S. Cl.
CPC ...
G01R 31/2837 (2012.12); G01R 31/287 (2012.12);
Abstract

A system for characterizing a transistor circuit which has a local minimum in its transfer characteristic by finding its local minimum. The system comprises: a bias voltage generator for generating a toggling signal; a multiplier configured for multiplying an electrical signal which is a function of the drain source current of the transistor circuit, with a waveform alternating between two predefined values synchronously with the toggling signal; a first integrator configured for integrating the electrical signal from the multiplier, and wherein if more integrators are present, linear combinations of output signals of the integrators are provided to the further integrators; a summator configured for summing the toggling signal and an integration signal and configured for outputting the sum to the gate of the transistor circuit.


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