The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2025
Filed:
Apr. 19, 2023
Applicant:
Guangzhou Tyrafos Semiconductor Technologies Co., Ltd, Guangzhou, CN;
Inventors:
Assignee:
Guangzhou Tyrafos Semiconductor Technologies Co., LTD, Guangzhou, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/78 (2022.12); G06F 1/08 (2005.12); H01L 25/075 (2005.12); H01L 25/18 (2022.12); H03K 19/0185 (2005.12); H03L 7/099 (2005.12); H04N 25/60 (2022.12); H04N 25/627 (2022.12); H04N 25/63 (2022.12); H04N 25/709 (2022.12); H04N 25/76 (2022.12); H04N 25/77 (2022.12); H04N 25/772 (2022.12); H04N 25/778 (2022.12); H10F 39/00 (2024.12);
U.S. Cl.
CPC ...
H04N 25/78 (2022.12); G06F 1/08 (2012.12); H01L 25/0753 (2012.12); H01L 25/18 (2012.12); H03K 19/018521 (2012.12); H03L 7/099 (2012.12); H04N 25/60 (2022.12); H04N 25/627 (2022.12); H04N 25/63 (2022.12); H04N 25/709 (2022.12); H04N 25/77 (2022.12); H04N 25/772 (2022.12); H04N 25/778 (2022.12); H04N 25/7795 (2022.12); H10F 39/026 (2024.12); H10F 39/8037 (2024.12); H10F 39/811 (2024.12);
Abstract
An image sensor and an operation method thereof are provided. The image sensor includes a pixel circuit and a column readout circuit. The pixel circuit includes a pixel unit, a transfer transistor, a reset transistor, a readout transistor and a selection transistor. The column readout circuit includes a first circuit node and a second circuit node. A first terminal of the first reset transistor and a first terminal of the first readout transistor are coupled to a first circuit node, and a second terminal of the first select transistor is coupled to a second circuit node.