The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Aug. 31, 2020
Applicant:

Plessey Semiconductors Limited, Plymouth, GB;

Inventors:

Andrea Pinos, Plymouth, GB;

Simon Ashton, Plymouth, GB;

Samir Mezouari, Plymouth, GB;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/15 (2005.12); H01L 33/00 (2009.12); H01L 33/32 (2009.12);
U.S. Cl.
CPC ...
H01L 27/156 (2012.12); H01L 33/0066 (2012.12); H01L 33/32 (2012.12);
Abstract

A method of forming a Light Emitting Diode (LED) precursor comprising: forming a first semiconducting layer comprising a Group III-nitride on a substrate, selectively removing a portion of the first semiconducting layer to form a mesa structure, and forming a monolithic LED structure. According to the method, the first semiconducting layer has a growth surface on an opposite side of the first semiconducting layer to the substrate. According to the method, the first semiconducting layer is selectively removed to form the mesa structure such that the growth surface of the first semiconducting layer comprises a mesa surface and a bulk semiconducting surface. Further, the monolithic LED structure is formed on the growth surface of the first semiconducting layer such that the monolithic LED structure covers the mesa surface and the bulk semiconducting surface, the monolithic LED structure comprising a plurality of layers, each layer comprising a Group III-nitride, including a second semiconducting layer, an active layer provided on the second semiconducting layer, the active layer configured to generate light, and a p-type semiconducting layer provided on the active layer. A potential barrier is provided between a first portion of the p-type semiconducting layer covering the mesa surface and a second portion of the p-type semiconducting layer covering the bulk semiconducting surface. The potential barrier surrounds the first portion of the p-type semiconducting layer covering the mesa surface.


Find Patent Forward Citations

Loading…