The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2025
Filed:
Jun. 12, 2023
Applicant:
Nanya Technology Corporation, New Taipei, TW;
Inventors:
Wei-Zhong Li, Taoyuan, TW;
Hsih-Yang Chiu, Taoyuan, TW;
Assignee:
NANYA TECHNOLOGY CORPORATION, New Taipei, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/525 (2005.12); H01L 23/528 (2005.12); H10D 30/01 (2024.12); H10D 30/60 (2024.12); H10D 62/13 (2024.12); H10D 64/01 (2024.12); H10D 64/23 (2024.12); H10D 64/27 (2024.12); H10D 84/01 (2024.12); H10D 84/03 (2024.12); H10D 84/40 (2024.12); H10D 84/83 (2024.12);
U.S. Cl.
CPC ...
H01L 23/5256 (2012.12); H01L 23/5283 (2012.12); H10D 62/151 (2024.12); H10D 64/258 (2024.12); H10D 64/512 (2024.12); H10D 84/0133 (2024.12); H10D 84/0149 (2024.12); H10D 84/0151 (2024.12); H10D 84/038 (2024.12); H10D 84/83 (2024.12);
Abstract
The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a transistor disposed over the substrate; and a trench fuse disposed in the substrate and penetrating a source/drain (S/D) region of the transistor. A method for manufacturing the semiconductor structure is also provided.