The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Jul. 25, 2023
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Ryu Ogiwara, Yokohama, JP;

Hidehiro Shiga, Yokohama, JP;

Daisaburo Takashima, Yokohama, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2005.12); G11C 5/02 (2005.12); H10B 63/00 (2022.12);
U.S. Cl.
CPC ...
G11C 5/063 (2012.12); G11C 5/025 (2012.12); H10B 63/34 (2023.01); H10B 63/84 (2023.01);
Abstract

According to one embodiment, in a semiconductor memory device, multiple first memory cells are connected in parallel between a first local bit line and a local source line. Multiple second memory cells are connected in parallel between a second local bit line and the local source line. Each of the multiple first memory cells includes a first cell transistor and a first resistance change element connected in series. Each of the multiple second memory cells includes a second cell transistor and a second resistance change element connected in series. A first selection gate line extends in a second direction across multiple cell blocks arranged in the second direction. A second selection gate line is placed on the opposite side of the first selection gate line with the local source line interposed therebetween. The second selection gate line extends in the second direction across multiple cell blocks arranged in the second direction.


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