The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Dec. 14, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ashim Dutta, Clifton Park, NY (US);

Dominik Metzler, Clifton Park, NY (US);

Oscar van der Straten, Guilderland Center, NY (US);

Theodorus E. Standaert, Clifton Park, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2005.12); G11C 11/00 (2005.12); G11C 11/16 (2005.12); H01L 23/522 (2005.12); H10B 61/00 (2022.12); H10N 50/01 (2022.12); H10N 50/10 (2022.12); H10N 50/80 (2022.12); H10N 50/85 (2022.12);
U.S. Cl.
CPC ...
G11C 11/161 (2012.12); H01L 23/5226 (2012.12); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01);
Abstract

A memory device with modified top electrode contact includes a memory pillar composed of a bottom electrode, a magnetic random-access memory (MRAM) stack above the bottom electrode, and a top electrode above the MRAM stack. A first portion of an encapsulation layer is disposed along opposite sidewalls of the bottom electrode, on opposite sidewalls of the MRAM stack and on opposite sidewalls of a bottom portion of the top electrode, a second portion of the encapsulation layer is located above a second dielectric layer. A metal cap is located above an uppermost surface and opposite sidewalls of a top portion of the top electrode and above an uppermost surface of the first portion of the encapsulation layer. A second conductive interconnect is formed above a top surface of the metal cap wrapping around opposite sidewalls of the first portion of the encapsulation layer and opposite sidewalls of the metal cap.


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