The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Jun. 30, 2022
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Jiangnan Lu, Beijing, CN;

Libin Liu, Beijing, CN;

Zhenzhen Shan, Beijing, CN;

Shiming Shi, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/32 (2015.12); G09G 3/3225 (2015.12); G09G 3/3258 (2015.12); H10K 59/121 (2022.12);
U.S. Cl.
CPC ...
G09G 3/3258 (2012.12); G09G 3/3225 (2012.12); H10K 59/1213 (2023.01); G09G 2300/0452 (2012.12); G09G 2300/0819 (2012.12); G09G 2300/0842 (2012.12); G09G 2300/0852 (2012.12); G09G 2310/062 (2012.12); G09G 2310/08 (2012.12); G09G 2320/0233 (2012.12); G09G 2320/0247 (2012.12); G09G 2320/045 (2012.12); G09G 2330/021 (2012.12);
Abstract

Provided are a pixel driving circuit and a display panel. The pixel driving circuit includes: a data writing sub-circuit, a threshold compensation sub-circuit, a driving sub-circuit, a storage sub-circuit, a first reset sub-circuit, a second reset sub-circuit. The driving sub-circuit and the storage sub-circuit are connected at a first node; the data writing sub-circuit and the storage sub-circuit are connected at a second node; the first reset sub-circuit includes a first transistor having a control electrode connected with a first reset signal line, a first electrode connected with a first initialization signal line, and a second electrode connected with the first node; the threshold compensation sub-circuit includes a second transistor having a first electrode connected with the first node, a second electrode connected with the second node, and a control electrode connected with a second scan line; the first transistor and/or the second transistor includes an oxide thin film transistor.


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