The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Mar. 29, 2022
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Binbin Tong, Beijing, CN;

Lizhong Wang, Beijing, CN;

Jianbo Xian, Beijing, CN;

Liping Lei, Beijing, CN;

Chunping Long, Beijing, CN;

Yunping Di, Beijing, CN;

Ce Ning, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2005.12); G02F 1/01 (2005.12); G02F 1/1333 (2005.12); G02F 1/1339 (2005.12); G02F 1/1343 (2005.12);
U.S. Cl.
CPC ...
G02F 1/136286 (2012.12); G02F 1/0107 (2012.12); G02F 1/133308 (2012.12); G02F 1/1339 (2012.12); G02F 1/13396 (2020.12); G02F 1/13439 (2012.12);
Abstract

At least one embodiment of the present disclosure provides a display panel, and the display panel includes: a first substrate and a second substrate oppositely combined with each other, the first substrate includes a base substrate, and a gate line, a first electrode, a first interlayer insulating layer, and second electrode on the base substrate; the first interlayer insulating layer includes a first via hole penetrating through the first interlayer insulating layer, the second electrode is electrically connected to the first electrode the first via hole, first support structure is provided in a region corresponding to the first via hole and on a side of the second electrode away from the base substrate; at least a part of the first support structure is located in the first via hole, an orthographic projection of the first via hole overlaps with an orthographic projection of the gate line on the base substrate.


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