The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2025
Filed:
Sep. 19, 2022
Siliconbrite Technologies, Inc., Santa Clara, CA (US);
Cameron Nathan Jackson, Los Gatos, CA (US);
Baris Karagozlu, Dublin, CA (US);
SiliconBrite Technology, Inc., Santa Clara, CA (US);
Abstract
A powerline load monitor has a voltage sense input, a current sense input, a clock input and a data output. It includes first and second ADCs coupled with the voltage sense and current sense input, and coupled with a serial interface. A power manager is coupled with the clock input, the ADCs, and the serial interface. When the power manager receives a first clock, it puts the powerline load monitor in active mode and starts a first timer with a first timeout time. The first and second ADC convert a sensed voltage and a sensed current to digital values for the serial interface. When the serial interface receives a trailing edge of a clock pulse, it outputs a data bit of the digital values. When the first timer times out, the power manager puts the powerline load monitor in a standby mode to save power.