The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Apr. 02, 2024
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Hajime Kimura, Atsugi, JP;

Atsushi Umezaki, Isehara, JP;

Shunpei Yamazaki, Setagaya, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1333 (2006.01); G02F 1/1334 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01); H01L 29/786 (2006.01); H10D 30/67 (2025.01); H10D 62/40 (2025.01); H10D 62/80 (2025.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 86/60 (2025.01); G02F 1/133345 (2013.01); G02F 1/1334 (2013.01); G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G09G 3/2007 (2013.01); G09G 3/36 (2013.01); H10D 30/67 (2025.01); H10D 30/6704 (2025.01); H10D 30/6756 (2025.01); H10D 30/6757 (2025.01); H10D 62/402 (2025.01); H10D 62/80 (2025.01); H10D 86/0221 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); G02F 1/133302 (2021.01); G02F 1/13345 (2021.01); G09G 2300/0426 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0252 (2013.01); G09G 2320/0257 (2013.01); G09G 2330/021 (2013.01); H10D 84/0128 (2025.01); H10D 84/038 (2025.01);
Abstract

An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less.


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