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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12274064 B1

PDFFull Text
Date of Patent:
Apr. 08, 2025

Filed:

May. 09, 2024

Semiconductor device, semiconductor wafer, memory device, and electronic device

Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Hajime Kimura, Atsugi, JP;

Tatsunori Inoue, Atsugi, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Attorneys:

Eric J. Robinson

Robinson Intellectual Property Law Office, P.C.

Primary Examiner:

Jose R Diaz

Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/20 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 29/24 (2013.01); H01L 29/40117 (2019.08); H01L 29/66969 (2013.01); H01L 29/7831 (2013.01); H01L 29/7889 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/20 (2023.02); H10B 43/35 (2023.02); H01L 21/02565 (2013.01); H01L 21/0262 (2013.01); H10B 43/40 (2023.02);
Abstract

An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.

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