The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Jan. 25, 2023
Applicant:

Graphcore Limited, Bristol, GB;

Inventors:

Simon Christian Knowles, Bristol, GB;

Stephen Felix, Bristol, GB;

Daniel John Pelham Wilkinson, Bristol, GB;

Assignee:

GRAPHCORE LIMITED, Bristol, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 45/60 (2022.01); G06F 13/16 (2006.01); G06F 15/163 (2006.01); G06F 15/78 (2006.01); H04L 45/00 (2022.01);
U.S. Cl.
CPC ...
H04L 45/60 (2013.01); G06F 13/1668 (2013.01); G06F 15/163 (2013.01); G06F 15/7825 (2013.01); H04L 45/566 (2013.01);
Abstract

A memory attachment and routing chip includes a single die having a set of external ports; at least one memory attachment interface comprising a memory controller to attach to external memory, and a fabric core in which routing logic is implemented. The routing logic can (i) receive a first packet of a first type from a first port of the set of ports, the first type of packet being a memory access packet with a memory address which lies in a range of memory addresses associated with the memory attachment and routing chip, detect the memory address and route the packet of the first type to the memory attachment interface. The routing logic can (ii) receive a second packet of a second type, the second type of packet being an inter-processor packet comprising a destination identifier identifying a processing chip external to the memory attachment.


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