The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Apr. 19, 2021
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

John B. Bowlerwell, Dunfermline, GB;

Andrew J. Howlett, Edinburgh, GB;

Saurabh Singh, Edinburgh, GB;

Andrew Buist, Edinburgh, GB;

Assignee:

Cirrus Logic Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/14 (2006.01); G06F 1/18 (2006.01); H02M 3/156 (2006.01); H03F 1/52 (2006.01); H03G 1/00 (2006.01);
U.S. Cl.
CPC ...
H03G 1/0029 (2013.01); G06F 1/189 (2013.01); H02M 3/156 (2013.01); H03F 1/52 (2013.01);
Abstract

The present disclosure relates to circuitry for providing an output voltage. The circuitry comprises: voltage generator circuitry configured to provide an output voltage to an output node of the circuitry; current limiter circuitry operable to perform current limiting so as to limit a current supplied at the output node of the circuitry; detection circuitry configured to output a detection signal when a load voltage across a load coupled to the output node of the circuitry reaches a target voltage; and delay circuitry configured to receive the detection signal and to output a control signal to deactivate current limiting by the current limiter circuitry after a predetermined delay period after receiving the detection signal.


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