The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Jun. 07, 2023
Applicant:

Rivian Ip Holdings, Llc, Irvine, CA (US);

Inventors:

Young Mok Doo, La Palma, CA (US);

Juan Lopez, Wildomar, CA (US);

Shawn Merritt, Lomita, CA (US);

Assignee:

Rivian IP Holdings, LLC, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01); H02M 7/00 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H02M 7/003 (2013.01); H05K 1/0256 (2013.01); H05K 3/303 (2013.01); H05K 2203/167 (2013.01);
Abstract

Disclosed embodiments include alignment apparatuses for circuit boards, inverter assemblies, and methods for fabricating an assembly with a circuit board placed on an alignment apparatus. An illustrative apparatus includes an electrically insulative substrate having a first substantially planar surface and a second substantially planar surface forming an opposing side of the first substantially planar surface. The second substantially planar surface defines therein self-aligning features that are configured to align at least one power module pin with the electrically insulative substrate. The first substantially planar surface has at least one alignment feature configured to align a printed circuit board with the electrically insulative substrate. The apparatus also includes a routing feature coupled to the electrically insulative substrate. The routing feature is configured to route at least one low voltage conductor.


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