The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Apr. 12, 2021
Applicants:

National Institute of Advanced Industrial Science and Technology, Tokyo, JP;

National University Corporation Kanazawa University, Ishikawa, JP;

Inventors:

Hiromitsu Kato, Ibaraki, JP;

Masahiko Ogura, Ibaraki, JP;

Toshiharu Makino, Ibaraki, JP;

Satoshi Yamasaki, Ibaraki, JP;

Tsubasa Matsumoto, Ishikawa, JP;

Norio Tokuda, Ishikawa, JP;

Takao Inokuma, Ishikawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/41 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78 (2013.01); H01L 29/1602 (2013.01); H01L 29/41 (2013.01);
Abstract

The present invention provides a novel semiconductor device for high breakdown voltage having no drift layer. The semiconductor device includes a first semiconductor layer of a first conductivity type which is either a p-type or an n-type conductivity type, a source portion arranged so as to be in contact with the first semiconductor layer and configured as a semiconductor portion of a second conductivity type different from the first conductivity type, a source electrode arranged in ohmic contact with the source portion, a gate electrode arranged on at least one selected from surfaces of the first semiconductor layer via a gate insulating film interposed therebetween and capable of forming by an applied electric field, an inversion layer in a region of the first semiconductor layer near the surface of the first semiconductor layer contacting the gate insulating film, a second semiconductor layer of the first conductivity type arranged so as to be in contact with the inversion layer, and a drain electrode separated from the inversion layer and arranged in Schottky contact with the second semiconductor layer.


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