The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2025
Filed:
Apr. 14, 2022
Samsung Electronics Co., Ltd., Suwon-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Abstract
Provided is a three-dimensionally (3D) stacked semiconductor chip architecture including a first semiconductor chip including a first wafer, a first front-end-of-line (FEOL) layer provided on a first side of the first wafer, a first middle-of-line (MOL) layer provided on the first FEOL layer, a first back-end-of-line (BEOL) layer provided on the first MOL layer, a first power rail layer provided on a second side of the first wafer, and a second semiconductor chip including a second wafer, a second FEOL layer provided on a first side of the second wafer, a second MOL layer provided on the second FEOL layer, a second BEOL layer provided on the second MOL layer, a second power rail layer provided on a second side of the second wafer, wherein the first power rail layer and the second power rail layer contact each other.