The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Apr. 13, 2022
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventor:

Yaojian Leng, Vancouver, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01F 17/00 (2006.01); H01F 27/28 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10D 1/20 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); H01F 17/0013 (2013.01); H01F 27/2823 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H10D 1/20 (2025.01); H01F 2017/002 (2013.01); H01F 2017/0073 (2013.01); H01F 2017/0086 (2013.01);
Abstract

A device includes (a) an integrated inductor having an inductor wire and (b) a metal interconnect arrangement, both formed in an integrated circuit layer stack of alternating metal layers and via layers. At least a portion of the inductor wire is defined by an inductor element stack including multiple metal layer inductor elements formed in multiple respective metal layers, and multiple via layer inductor elements formed in multiple respective via layers and conductively connected to the metal layer inductor elements. Each via layer inductor element has a length of at least 1 μm in each of two lateral directions orthogonal to each other and perpendicular to the vertical direction. The metal interconnect arrangement includes metal layer interconnect elements formed in the respective metal layers, and interconnect vias formed in the respective via layers.


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