The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Feb. 28, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Tae-Hong Kwon, Suwon-si, KR;

Kiwhan Song, Suwon-si, KR;

Gyosoo Choo, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 16/04 (2006.01); G11C 16/20 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/0433 (2013.01); G11C 16/20 (2013.01);
Abstract

Various example embodiments provide a flash memory device, comprising a cell string; a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell by precharging a sensing node connected to the bit line; and a voltage regulator. The page buffer comprises a latch including first and second inverters coupled between a latch node and an inverted latch node; and a pull-down NMOS transistor for tripping the sensing result of the selected memory cell to the latch node. The voltage regulator adjusts a trip voltage by providing the source voltage to the pull-down NMOS transistor. The flash memory device reduce a trip voltage variation range by using only the pull-down NMOS transistor characteristics. Also, an OFF cell margin and an ON cell margin may be secured by adjusting the level of the trip voltage using the source voltage.


Find Patent Forward Citations

Loading…