The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Oct. 24, 2023
Applicant:

Silicon Motion, Inc., Zhubei, TW;

Inventor:

Shen-Ting Chiu, Miaoli County, TW;

Assignee:

SILICON MOTION, INC., Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0625 (2013.01); G06F 3/0679 (2013.01);
Abstract

The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for executing host write commands. The method performed by a processing unit includes: providing a sequential-write command queue (SCQ), a random-write command queue (RCQ) and a mark queue; when a specific condition is met, obtaining a first logical address range carried in the conflicting sequential write command and second logical address ranges carried in the sequential write commands earlier than the conflicting sequential write command from the SCQ, and/or a third logical address range carried in the conflicting random write command and fourth logical address ranges carried in the random write commands earlier than the conflicting random write command from the RCQ according to content of the record; reading user data of the first logical address range from a first address of the RAM and user data of the second logical address ranges from second addresses of the RAM, and/or user data of the third logical address range from a third address of the RAM and user data of the fourth logical address ranges from fourth addresses of the RAM; and programming the user data of the first logical address range and the second logical address ranges, and/or the user data of the third logical address range and the fourth logical address ranges into the flash module.


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