The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2025
Filed:
Jul. 19, 2023
Applicant:
Lodestar Licensing Group Llc, Burlingame, CA (US);
Inventor:
Gil Golov, Backnang, DE;
Assignee:
Lodestar Licensing Group LLC, Evanston, IL (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G05D 1/00 (2006.01); G05D 1/646 (2024.01); G06F 9/4401 (2018.01); G06F 11/07 (2006.01); G06F 12/0804 (2016.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0804 (2013.01); G05D 1/0212 (2013.01); G05D 1/646 (2024.01); G06F 9/4418 (2013.01); G06F 11/0727 (2013.01); G06F 11/0751 (2013.01); G06F 11/079 (2013.01); G06F 11/0793 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/205 (2013.01);
Abstract
A computing system has a processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. The computing system is configured to: monitor use of the memory regions in volatile memory; based on monitoring the use of the memory regions, identify at least one of the memory regions of the volatile memory; initiate a hibernation process; and during the hibernation process, copy data stored in the identified memory regions to non-volatile memory.