Detection circuit and detection method

Abstract

A detection circuit configured to detect whether timing violations occur in a target circuit. The target circuit is operated according a clock signal. The detection circuit includes a signal generation circuit, a first delay adjustable circuit, a second delay adjustable circuit, and a signal detector. The signal generation circuit is configured to generate a test signal. The first and second delay adjustable circuit are respectively configured to delay the test signal and clock signal to generate a first delay signal and a second delay signal according to the operating speed of the target circuit. The signal detector is configured to generate an indicating signal according to the first delay signal, the second delay signal, the test signal, and the clock signal. The indicating signal is configured to indicate whether an operating voltage of the target circuit causes a hold time violation of timing violations to occur in the target circuit.