The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Sep. 24, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Shogo Mochizuki, Mechanicville, NY (US);

Nicolas Loubet, Guilderland, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/69 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 30/797 (2025.01); H10D 30/031 (2025.01); H10D 30/6757 (2025.01); H10D 84/017 (2025.01); H10D 84/0184 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 30/6735 (2025.01);
Abstract

Embodiments of the invention are directed to a semiconductor-based structure that includes a stack having spaced-apart non-sacrificial nanosheets. A source or drain (S/D) trench is adjacent to the stack, wherein the S/D trench includes a bottom surface and sidewalls. A S/D template layer includes a continuous layer of a first type of semiconductor material, wherein the S/D template layer is within a portion of the S/D trench, on the bottom surface of the S/D trench, and on the sidewalls of the S/D trench. A doped S/D region is on the S/D template layer and within the S/D trench. In some aspects of the invention, the doped S/D region includes a second type of semiconductor material configured to induce strain in the spaced-apart non-sacrificial nanosheets.


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