The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Oct. 18, 2022
Applicant:

Lextar Electronics Corporation, Hsinchu, TW;

Inventor:

Ming-Jing Lee, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H01L 33/02 (2010.01); H01L 33/06 (2010.01); H01L 33/08 (2010.01); H01L 33/14 (2010.01); H01L 33/18 (2010.01); H01L 33/20 (2010.01); H01L 33/24 (2010.01); H01L 33/32 (2010.01); H01L 33/44 (2010.01); H01L 33/46 (2010.01); H01L 33/52 (2010.01); H01L 33/54 (2010.01); H01L 33/60 (2010.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); H05K 1/115 (2013.01); H05K 2201/09227 (2013.01); H05K 2201/10106 (2013.01); H05K 2201/10121 (2013.01); H05K 2201/10484 (2013.01); H05K 2201/10628 (2013.01);
Abstract

An electronic component sub-mount includes a body having a top surface, a bottom surface, and a supporting surface. The top and bottom surfaces are located on opposite sides of the body. The supporting surface is located on one side of the body, and an angle that is not equal to 0 degrees is formed between the supporting surface and the bottom surface. A first conductive layer is disposed on the bottom surface and includes multiple first conductive lines. A second conductive layer is disposed on the supporting surface, extending to the top surface, and includes multiple second conductive lines. The second conductive lines on the supporting surface have a first pin layout, and the second conductive lines on the top surface have a second pin layout different from the first pin layout. The second pin layout matches the pin layout of first conductive lines on the bottom surface.


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