Multiplexed higher order sigma-delta analog-to-digital converter

Abstract

A multiplexed sigma-delta analog-to-digital converter (ADC) is provided for digitizing analog input signals of at least two input channels. The ADC includes input circuitry that obtains samples of the input channels and an integrator chain. The integrator chain includes a first delaying integrator and a second delaying integrator. The first delaying integrator processes a sample of one of the two input channels at a time. A first non-delaying integrator is disposed in the integrator chain either between the first delaying integrator and the second delaying integrator or after the second delaying integrator. A clocking arrangement includes a first clock set and a second clock set. Channel selection clocks included in the second clock set are delayed in comparison to the respective channel selection clocks included in the first clock set in order to prevent data from being mixed between consecutive full clock cycles.