The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Apr. 04, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Enis Tuncer, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 15/20 (2006.01); G01R 19/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H10N 52/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/49541 (2013.01); G01R 15/202 (2013.01); G01R 19/0092 (2013.01); H01L 21/4803 (2013.01); H01L 21/56 (2013.01); H01L 23/3107 (2013.01); H01L 24/05 (2013.01); H01L 24/85 (2013.01); H10N 52/101 (2023.02); H01L 24/48 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/48175 (2013.01);
Abstract

In a described example, an apparatus includes: a lead frame having a first portion and having a second portion electrically isolated from the first portion, the first portion having a side surface normal to a planar opposite surface, and having a recessed edge that is notched or chamfered and extending between the side surface and a planar device side surface; a spacer dielectric mounted to the planar device side surface and partially covered by the first portion, and extending beyond the first portion; a semiconductor die mounted to the spacer dielectric, the semiconductor die partially covered by the spacer dielectric and extending beyond the spacer dielectric; the second portion of the lead frame comprising leads coupled to the semiconductor die by electrical connections; and mold compound covering the semiconductor die, the electrical connections, the spacer dielectric, and partially covering the first portion and the second portion.


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