The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Nov. 20, 2023
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Chengdu, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Hongting Lu, Beijing, CN;

Yuhsiung Feng, Beijing, CN;

Xin Mou, Beijing, CN;

Chenyu Chen, Beijing, CN;

Shuang Zhao, Beijing, CN;

Zhongliu Yang, Beijing, CN;

Jing Yang, Beijing, CN;

Wenbo Chen, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); H10K 59/131 (2023.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); H10K 59/1315 (2023.02); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0452 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0272 (2013.01); G09G 2310/08 (2013.01); G09G 2320/043 (2013.01); G09G 2330/026 (2013.01);
Abstract

A display substrate and a display device. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate, each sub-pixel includes a pixel circuit, and the pixel circuit includes a drive sub-circuit and a first reset sub-pixel. The first reset sub-pixel is configured to apply a first reset voltage to a control terminal of the drive sub-circuit in response to a first reset control voltage; the display substrate further comprises a first reset signal line electrically connected with the first terminal of the first reset sub-circuit to provide the first reset voltage, and the first reset signal line is in a semiconductor layer and comprises a doped semiconductor material.


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