The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Dec. 16, 2022
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Eashwar Thiagarajan, Bothell, WA (US);

Andrew Page, Kirkland, WA (US);

Harold Kutz, Edmonds, WA (US);

Kendall Castor-Perry, Seattle, WA (US);

Rajiv Singh, Bothell, WA (US);

Erhan Hancioglu, Shoreline, WA (US);

Bert Sullam, Bellevue, WA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); G06F 13/28 (2006.01); H03F 3/189 (2006.01); H03F 3/72 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1736 (2013.01); G06F 13/28 (2013.01); H03F 3/189 (2013.01); H03F 3/72 (2013.01); H03M 1/1245 (2013.01);
Abstract

Implementations disclosed describe an integrated circuit (IC) having a plurality of reconfigurable analog circuits that include a finite state machine (FSM) logic circuit and further include an interface to receive an input signal. In a first IC configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the IC may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the FSM logic circuit processing the first output value, the IC may reconfigure the plurality of reconfigurable analog circuits into a second IC configuration having a second configuration setting.


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